1. Field of the Invention
This invention generally relates to data processing systems and more specifically to the refreshing of information stored in a main memory comprising dynamic semiconductor random access memory chips in such a system.
2. Discussion of Background
Data processing system main memories are used to store both programs (software instructions) and data (operands). Main memories come in a variety of forms. The form of the memory will determine whether the information contained therein can be accessed sequentially or randomly. The two types of random access main memory that are most common today are magnetic core memories and semiconductor memories. In a magnetic core memory, the contents of the memory are not lost when power is turned off and the information contained therein can be retrieved and modified after the restoration of the power to the data processing system containing a magnetic core main memory. However, the contents of most semiconductor random access memory (RAM) are lost when power is turned off. If permanent program storage is required, or if it is inconvenient to reload a main memory after power outages, a battery backup unit may be included within the system to maintain power to the RAM during periods of power outage.
There are two main classes of semiconductor RAM in use today: static and dynamic. Dynamic RAMs require special controls circuitry to refresh their contents during operation. However, dynamic RAMs can be more highly integrated than static RAMs and they use less power and are therefore less expensive for large memories. Static RAMs do not require refresh circuitry and are thus less expensive for small memories.
Most of the 4K and 16K (1K=1024) dynamic RAM chips available today specify that each bit cell within the RAM chip must be refreshed every two milliseconds. A 4K dynamic RAM chip has its bit cells arranged in arrays of 64 rows and 64 columns. All columns in a single row within a RAM chip are refreshed simultaneously so that only 64 refresh cycles, each with a different row address, need be performed each two milliseconds. The 16K bit dynamic memories have their bit cells arranged in arrays of 128 rows and 128 columns. Again all columns in a single row in the RAM chip are refreshed simultaneously. This means that 128 refresh cycles, each with a different row address, must be supplied during each two milliseconds. For 4K RAM chips, a 6-bit refresh row address counter can be used to supply refresh row addresses and for 16K bit RAM chips, a 7-bit counter can be used to supply refresh row addresses. The refresh row address counter must be incremented after each refresh cycle. Refresh cycles for a dynamic RAM may be a set of contiguous cycles known as burst-mode refresh, or they may be discreet non-adjacent memory cycles known as distributed or single cycle refresh. One method or the other may be chosen based on main memory availability requirements and ease of overall system design. In either case, some means must be provided to arbitrate between CPU initiated memory read and memory write cycles, and main memory initiated refresh cycles.
There are three methods in use today to refresh dynamic RAMs. Each method differs slightly in complexity, generality and memory availability. The asynchronous method assumes that memory refresh is a real time event, one memory refresh cycle every fifteen microseconds (128 cycles every two milliseconds for a 16K RAM) and is independent of the state of the CPU. The asynchronous method yields system flexibility since it is very loosely coupled. A system using the asynchronous memory refresh method normally has dedicated control logic in the main memory which may run independently of the CPU. The logic supplies memory refresh cycles as needed and couples with the CPU only to provide read or write cycles. In the asynchronous method, the memory system is usually unaware of the state of the CPU and operates asynchronously with respect to CPU timing signals. Using the asynchronous refresh method, the CPU must be designed to be tolerant of occasionally having to wait for the memory to perform a refresh cycle when the CPU attempts to perform a memory read or write cycle. Use of the asynchronous memory refresh method may lead to a high degree of complexity which degrades overall system performance because an arbitrator must be provided between the asynchronous refresh cycles and the CPU memory read and write cycles. The problem is further complicated since the beginning of a memory read or write cycle must be delayed until the conflicting requests for memory have been resolved and the appropriate memory address, data and control line set-up times have been supplied. The memory refresh resolution time adds directly to the system access time for each memory cycle.
The synchronous method of refresh, on the other hand, can improve the performance and apparent availability of the memory system to the CPU. Refresh cycles are forced to occur synchronously with CPU events and events are usually chosen in a memory cycle in which the CPU won't be accessing the main memory. Therefore, there is no contention for the main memory and the refresh cycles do not detract from the apparent memory availability. This hiding of the memory refresh cycles, when the memory would otherwise be idle, is often called invisible refresh since the CPU receives no delay due to refresh. As a result, the main memory is available to the CPU without conflict every time the memory is requested. The heart of an efficient synchronous refresh memory system is a refresh scheduler that accepts status inputs from a refresh timer and the CPU and based on its knowledge of the CPU, schedules the refresh cycles into idle portions of the CPU cycle. An override must be provided to guarantee refresh, should the CPU be detained from reaching the normal refresh event, such as when the CPU enters a halt or wait state. An override may introduce some asynchronism back into the system, for the CPU may begin again at any time.
Semisynchronous refresh is a combination of asynchronous and synchronous refresh. The semisynchronous method simplifies an asynchronous system's request arbitrator, by having the memory request initiated synchronously with a clock edge. Thus, if the refresh request is synchronous with the opposite clock edge, the two request transitions will never occur simultaneously. Except for the synchronization of memory refresh requests with the CPU clock, semisynchronous refresh is very similar to asynchronous refresh. There must still be memory read or write cycle versus memory refresh cycle arbitration logic since one memory cycle may already in progress when the other type of memory cycle is requested. However, this arbitrational logic can be simpler using the semisynchronous refresh method. Further, the memory controller must still arbitrate between requests and lock out the tardy memory request. Hence, memory refresh is still visible to the CPU, and the CPU may have to wait for the refresh cycle to be completed before gaining access to the memory.
A recent article dealing with interfacing dynamic RAMs with microprocessors entitled "Keep the Memory Interface Simple" by Gary Fielland and Ken Oishi may be found in the Apr. 26, 1978 issue of Electronic Design, 9.